aiT WCET Analyzers: Screenshots

aiT's user interface: source, disassembly, and message windows.

aiT analysis results: the computed WCET is given in CPU cycles. In the graphical representation of the call graph, additional timing details can be shown as desired.

Analysis details: WCET contribution per context.

The worst-case execution path is marked using a customizable color.

aiT for ARM7 TDMI, basic block graph view. For each edge, sum # describes the maximal number of traversals in the worst case. max t describes the maximum execution time of the basic block from which the edge originates. For each instruction, the set of all possible pipeline states can be shown as desired.

aiT for ColdFire 5307: Map of the formal pipeline model used for timing validation.

aiT for PowerPC 755: the behavior of cache and pipeline over time. Each horizontal layer corresponds to one CPU cycle. Branches in the tree represent different execution scenarios, e.g. a cache hit and a cache miss at a memory access if both cases have to be analyzed. aiT automatically checks all possibilities.

aiT for MPC5xx: visualization of pipeline analysis results for one instruction. Each yellow or green subgraph corresponds to a single pipeline state. Subgraph nesting operations offered by the integrated graph browser provide for interactive inspection of CPU and CPU core states at arbitrary points.