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Analysis details: WCET contribution per context. |
The worst-case execution path is marked using a customizable color. |
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aiT for PowerPC 755: the behavior of cache and pipeline over time. Each horizontal layer corresponds to one CPU cycle. Branches in the tree represent different execution scenarios, e.g. a cache hit and a cache miss at a memory access if both cases have to be analyzed. aiT automatically checks all possibilities. |
aiT for MPC5xx: visualization of pipeline analysis results for one instruction. Each yellow or green subgraph corresponds to a single pipeline state. Subgraph nesting operations offered by the integrated graph browser provide for interactive inspection of CPU and CPU core states at arbitrary points. |
| aiT for MPC5xx: Pipeline analysis results legend. | |||
| 1: Start state* 2: Intermediate state* 3: End state* 4: State description |
5: Flash A 6: Flash B 7: Memory controller 8: L2U |
9: Fetch 10: Dispatch 11: Execute 12: Write-back |
13: Decode buffer 14: Prefetch queue 15: History queue |
| * Relative to the instruction to be analyzed. | |||