Dr. Daniel K&aml;stner

Curriculum vitæ

Daniel Kästner, born in 1973, studied computer science and business economics at the Saarland University. In 1997, he completed his master’s thesis about code gen­eration methods for digital signal processors, for which he received the 1999 VDI Saar Award.

From 1997 to 2000, he received a doctoral scholarship in the Graduate Research Program “Efficiency and Complexity of Al­gorithms and Computer Systems” funded by the German Re­search Foundation. In 2000, he completed his Ph.D. thesis (summa cum laude) about code optimization for embedded processors, for which he received the SaarLB Science Award in 2002.

Dr. Kästner is a co-founder of AbsInt. From 2000 to 2003, he was a research associate at Saarland Uni­versity and Senior Software Engineer with AbsInt. Since 2003, he is CTO at AbsInt.

2007 and 2012 he was a guest lecturer at Saarland University with advanced courses on the development of safety-critical embedded systems.

Dr. Kästner was a program commitee member of nu­merous in­ternational conferences, including:

Research interests

  • Functional safety
  • Program analysis
  • WCET analysis
  • Run-time error analysis
  • Code generation and optimization
  • Microprocessor modeling
  • Task scheduling for real-time systems
  • Just-in-time compilation
  • Abstract interpretation
  • Java virtual machines

Selected publications

  • D. Kästner, M. Schlickling, M. Pister, C. Cullmann, G. Gebhard, R. Heckmann, C. Ferdinand. Meeting Real-Time Requirements with Multi-Core Processors. Safecomp 2012 Workshop: Next Generation of System Assurance Approaches for Safety-Critical Systems (SASSUR), Magdeburg, September 2012.
  • D. Kästner, C. Ferdinand. Safety Standards and WCET Analysis Tools. Embedded Real Time Software and Systems Congress ERTS², Toulouse, 2012.
  • M. Dierkes, D. Kästner. Transferring Stability Proof Obligations from Model Level to Code Level. Embedded Real Time Software and Systems Congress ERTS², Toulouse, 2012.
  • D. Kästner, C. Ferdinand. Efficient Verification of Non-Functional Safety Properties by Abstract Interpretation: Timing, Stack Consumption, and Absence of Runtime Errors. Proceedings of the 29th International System Safety Conference ISSC2011, Las Vegas, 2011.
  • D. Kästner, C. Ferdinand, R. Heckmann, M. Jersak, P. Gliwa. An Integrated Timing Analysis Methodology for Real-Time Systems. SAE World Congress 2011.
  • D. Kästner, C. Ferdinand. Using Code Analysis Tools for Software Certification. Embedded World Congress 2011, Nürnberg, 2011.
  • D. Kästner, S. Wilhelm, S. Nenova, P. Cousot, R. Cousot, J. Feret, L. Mauborgne, A. Miné, X. Rival. Finding all Runtime Errors in C-Code. Embedded World Congress 2011, Nürnberg, 2011.
  • D. Kästner, R. Heckmann, C. Ferdinand. 100% Coverage for Safety-Critical Software — Efficient Testing by Static Analysis. Proceedings of the 29th International Conference on Computer Safety, Reliability and Security (SAFECOMP), Vienna, 2010.
  • D. Kästner, S. Wilhelm, S. Nenova, P. Cousot, R. Cousot, J. Feret, L. Mauborgne, A. Miné, X. Rival. Astrée: Proving the Absence of Runtime Errors. Embedded Real Time Software and Systems Congress ERTS², Toulouse, 2010.
  • C. Ferdinand, R. Heckmann, M. Jersak, D. Kästner, K. Richter. Integration of Code-Level and System-Level Timing Analysis for Early Architecture Exploration and Reliable Timing Verification. Embedded Real Time Software and Systems Congress ERTS², Toulouse, 2010.
  • C. Ferdinand, R. Heckmann, D. Kästner, S. Nenova. Architecture Exploration and Timing Estimation During Early Design Phases. Embedded World Congress, Nuremberg, 2010.
  • D. Kästner. Nachweis der Abwesenheit von Laufzeitfehlern mit Astrée. Design & Elektronik, 2010.
  • P. Gliwa, D. Kästner, M. Jersak. Das Zeitverhalten von Echtzeitsystemen im Griff. ElektronikPraxis Marktreport Embedded Systeme, February 2010.
  • S. Nenova, D. Kästner. Worst-Case Timing Estimation and Architecture Exploration in Early Design Phases. Proceedings of the 9th International Workshop on Worst-Case Execution-Time Analysis, Dublin, 2009.
  • D. Kästner, C. Ferdinand, S. Wilhelm, S. Nenova, O. Honcharova, P. Cousot, R. Cousot, J. Feret, L. Mauborgne, A. Miné, X. Rival, E.-J. Sims. Astrée: Nachweis der Abwesenheit von Laufzeitfehlern. Proceedings of the GI workshop “Entwicklung zuverlässiger Software-Systeme”, Vol. 29 of Softwaretechnik-Trends, Regensburg, August 2009.
  • D. Kästner. Vermeiden von Laufzeitfehlern in eingebetteter Software. atp Edition Automatisierungstechnische Praxis 10–11/2009, Oldenbourg Industrieverlag.
  • P. Gliwa, D. Kästner, K. Richter. Entwicklungsmethodik für zuverlässige, kostenoptimierte Echtzeitsysteme. 1st Elektronik automotive congress, Munich, 2009.
  • D. Kästner, C. Ferdinand. Timing Predictability of Embedded Systems. Embedded World Congress, Nuremberg, 2009.
  • D. Kästner, R. Wilhelm, R. Heckmann, M. Schlickling, M. Pister, M. Jersak, K. Richter, C. Ferdinand. Timing Validation of Automotive Software. 3rd International Symposium on Leveraging Applications of Formal Methods, Verification and Validation (ISOLA), Kassandra, Greece, 2008.
  • C. Ferdinand, R. Heckmann, and D. Kästner. Static Memory and Timing Analysis of Embedded Systems Code. Proceedings of The IET Conference on Embedded Systems at Embedded Systems Show (ESS) 2006, Birmingham.
  • D. Kästner. Postpass Software Compaction. In: Caspar Grote, editor, Kfz-Elektronik: Begleittexte zum Entwicklerforum, 16. Mai 2006, Ludwigsburg. Poing, Design & Elektronik, 2006.
  • D. Kästner. Mehr Effizienz durch weniger Speicherbedarf. D&V Kompendium. Munich, Publish-Industry Verlag, 2005.
  • M. Pister and D. Kästner. Generic Software Pipelining at the Assembly Level. Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2005), ACM International Conference Proceeding Series 136, pages 50–61. New York, ACM Press, 2005.
  • D. Kästner. Compilation for Embedded Processors. European Summer School on Embedded Systems, 2003. MRTC Report no 119/2004. Mälardalens Högskola. ISSN 1404-3401.
  • N. Fritz, D. Kästner, F. Martin. Automatically Generating Value Analyzers for Assembly Code. Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES), San Jose, 2003.
  • Björn Decker, Daniel Kästner. Reconstructing Control Flow from Predicated Assembly Code. International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2003.
  • Daniel Kästner. TDL: A Hardware Description Language for Retargetable Postpass Optimizations and Analyses. ACM SIGPLAN/SIGSOFT Conference on Generative Programming and Component Engineering (GPCE), 2003.
  • C. Ferdinand, D. Kästner, F. Martin, M. Langenbach, M. Sicks, S. Wilhelm, N. Fritz, S. Thesing, F. Fontaine, H. Theiling, R. Wilhelm. Validierung des Zeitverhaltens von kritischer Echtzeit-Software. Workshop: Automotive SW Engineering & Concepts. 33. Jahrestagung der GI, Frankfurt/M. Informatik 2003 — Innovative Informatikanwendungen, Band 1 (ISBN 3-88579-363-6), Lecture Notes in Informatics (LNI), 2003.
  • B. De Bus, D. Kästner, D. Chanet, L. Van Put, and B. De Sutter. Post-Pass Compaction Techniques. Communications of the ACM, vol. 46, issue 8, pages 41–46, August 2003.
  • Daniel Kästner, Stephan Wilhelm. Generic Control Flow Reconstruction from Assembly Code. Proceedings of the ACM SIGPLAN Joined Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES’02) and Software and Compilers for Embedded Systems (SCOPES’02), Berlin, 2002.
  • Daniel Kästner. Compiler Optimizations by ILP-based Approximations. SIAM Conference on Optimization, Toronto, 2002.
  • Daniel Kästner, Sebastian Winkel. ILP-based Instruction Scheduling for IA-64. Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, Utah, 2001.
  • Daniel Kästner. ILP-based Approximations for Retargetable Code Optimization. Proceedings of the 5th International Conference on Optimization: Techniques and Applications (ICOTA 2001), Hong Kong, 2001.
  • Daniel Kästner. Retargetable Postpass Optimisation by Integer Linear Programming. PhD Thesis. Verlag Pirrot, Saarbrücken, 2000. ISBN 3-930714-55-8.
  • Daniel Kästner. PROPAN: A Retargetable System for Postpass Optimisations and Analyses. Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, Vancouver, CA, June 2000.
  • Daniel Kästner, Marc Langenbach. Code Optimization by Integer Linear Programming. Proceedings of the 8th International Conference on Compiler Construction, Amsterdam. LNCS 1575, pages 122–136, Springer, 1999.
  • Christian Ferdinand, Daniel Kästner, Marc Langenbach, Florian Martin, Michael Schmidt, Jörn Schneider, Henrik Theiling, Stephan Thesing, and Reinhard Wilhelm. Run-Time Guarantees for Real-Time Systems — The USES Approach.. Proceedings of the ATPS99, Paderborn, Germany.
  • Daniel Kästner, Stephan Thesing. Cache-Aware Pre-Runtime Scheduling. Journal of Real-Time Systems, vol. 17, 1999.
  • Daniel Kästner, Reinhard Wilhelm. Operations Research Methods in Compiler Backends. Journal of Mathematical Communications, 1999.
  • Daniel Kästner, Stephan Thesing. Cache Sensitive Pre-Runtime Scheduling. Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, Montreal, CA. LNCS 1474, pages 131–145, Springer, 1998.
  • Daniel Kästner, Marc Langenbach. Integer Linear Programming vs. Graph-Based Methods in Code Generation. Technical Report A/01/98. Saarland University, 1998.
  • Daniel Kästner. Instruktionsanordnung und Registerallokation auf der Basis ganzzahliger linearer Programmierung für den digitalen Signalprozessor ADSP-2106x. Master’s Thesis. Saarland University, 1997.
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