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“The comparison shows that the WCET [computed by aiT] typically is about 25% higher than the measured time for the same task, the real but non-calculable WCET being in between. Another comparison is worth to mention: the one between aiT’s results and those of Airbus’ traditional method. As predicted when the decision for using aiT was made, the figures obtained by the traditional approach are a lot higher than those produced by the aiT-based method. Actually the overestimation is such that the traditional figures are useless.”
The review was conducted with an early prototype of aiT in 2003. The tool’s accuracy has since improved much further.
In his master’s thesis titled “Static WCET Analysis of Task-Oriented Code for Construction Vehicles”, Daniel Sehlberg found that aiT overestimated the measured WCET by an average of only 16%. Volvo’s traditional approach overestimated the WCET of the same tasks by an average of 212%.
aiT supports tight integration with the ASCET modeling tools from ETAS. The user can start aiT directly from the ASCET project editor menu to perform a WCET analysis of the automatically generated ECU code.
The following table shows a comparison of maximal measured run times and WCETs predicted by aiT for a sample engine throttle control module. The module was specified in ASCET and compiled with the TASKING C compiler v7.5 for an ST10F269 microcontroller board. Run times were extracted from bus traces (iSYSTEMS ILA 128 logic analyzer). The experiment showed an average overestimation of only 3%.
|Procedure||Measured WCET||Computed by aiT||Overestimation|
The ARMulator is a processor simulator provided by ARM as part of the ARM development toolkit. It enables the developer to evaluate the behavior of a program for a certain ARM processor without using the actual hardware.
In an experiment performed by Daniel Sandell at the Mälardalen University, the WCET estimates provided by aiT were on average only 5% higher than the simulated results provided by ARMulator.
“The aiT tool produced in all cases estimates that were higher than the simulated results. We think this is positive, because it gives an indication that the WCET estimates are safe. It should finally be noted that the WCET estimates have been compared against another hardware model and not against the real hardware.”
In 2006, aiT participated in the first WCET Tool Challenge, organized by University of Mälardalen and sponsored by the ARTIST2 Network of Excellence on Embedded Systems Design. The aim of the challenge was to inspect and compare different approaches in analyzing the worst-case execution time. All available tools and prototypes able to determine safe upper bounds for the WCET of tasks have participated.
aiT was the only tool that started for three different real processor architectures. It was the only tool that was able to produce results for all test programs. The results of analyses by aiT were in most cases exceptionally precise. Finding in the challenge was, amongst others, that aiT allows for user-friendly WCET analysis, advises against unrealistic annotations, and provides tight WCET values.
|aiT||7–8%||17/17 (100%)||54%||simple, medium, very complex|
|Bound-T||n/a||13/17 (76%)||26%||simple, medium|
|Chronos||81–89%||13/17 (76%)||24%||simulated processor|
“aiT was able to handle every kind of benchmark and every test program that was tested in the Challenge. aiT is able to support WCET analysis even for complex processors. […] aiT demonstrates its leading position through all its features, which contribute to its position as an industry-strength tool, satisfying the requirements from industry as posed by EADS Airbus and proven by the accomplishment in various projects.”