This project develops an integrated solution for the co-design of hardware and software that simulates the resource usage of software systems during their development, even at early design stages. Thanks to an innovative combination of automated reverse engineering and simulated hardware platform tests, highly optimized code can be produced or re-compiled for each specific hardware configuration. This makes the development process fully transparent from the get-go, accelerates and simplifies the integration of new software components, and helps achieve a previously unseen balance between the economic benefits and the ecological sustainability of safety-relevant software systems.
Consortium: EFS, CARIAD, AbsInt, emmtrix, Tensor Embedded, Sysgo, NXP, Universities of Augsburg, Luebeck, Clausthal, and Cottbus-Senftenberg.
This project is working on a completely European, ITAR-free microcontroller for space applications, with a focus on small satellites, flight control and payload computers for the purposes of mission control, earth observation, navigation and other applications. The microcontroller will provide mechanisms for increased reliability and adaptability with respect to the needs of the space applications. In addition to the microcontroller, the required ITAR-free middleware, RTOS and toolchain will be made available. Consortium: IHP, Sysgo, AbsInt, RedCat Devices, Thales Alenia Space.
A civil-aviation project by the German Federal Ministry for Economic Affairs and Energy. The project aims to establish a DO-178C/DO-330 qualifiable toolchain for multicore software development. The toolchain includes CompCert and TimeWeaver. For demonstration, it is used to develop a TSO-C151b Terrain Avoidance and Warning System in accordance with DAL-C. Consortium: emmtrix, DLR, AbsInt, TU Clausthal, Validas.
Sponsored by the German Ministry for Education and Research, this project develops tool-assisted methods for automated recognition and rectification of security flaws in embedded systems that can be exploited for side-channel attacks. Consortium: AbsInt, FZI Karlsruhe, Kasper & Oswald.
This multinational EU-funded project aims to further expand and develop the RISC-V architecture such that it can compete with existing commercial alternatives. This open specification eliminates the need to learn and create unique ecosystems for each processor architecture, increasing productivity, security and transparency. The approach developed in the TRISTAN project will be holistic, covering both electronic design automation tools and the full software stack.
Consortium: NXP, Infineon, ST Microelectronics, CEA, Bosch, Siemens, Thales, Leonardo, MinRes, Technolution, AntMicro, Sysgo, AbsInt, Nokia, Yonga, Eclipse Foundation, Epos, Tampereen, Cargotec, CodaSip, aicas, VLSI Solution, Tensor Embedded, Irdeto, Royal Netherlands Aerospace Center, E4 Computer Engineering, Strohmayer Klaus, Accemic, Greenwaves Technologies, IMEC, Fraunhofer, Synthara, Universities of Twente, Turin, and Bologna, TUs of Munich, Darmstadt, Graz, and Zurich.
This project aims to strengthen the technology sovereignty in Germany, starting with the competence of German companies and universities in the field of processor technology and the associated supply chains for various edge applications. This will result in new processor architectures, innovative software, and special verification approaches, thus strengthening technology sovereignty for the entire ecosystem.
As a specific use case, Bosch developed a neural-network based audio-event detection model, which has been ported to a Pulpissimo-based SoC platform using components and software of the Scale4Edge ecosystem.
Consortium: Infineon, Altair, DLR, Bosch, FZI, EPOS, Sysgo, AbsInt, IHP, MinRes, HM Munich, Universities of Darmstadt, Dresden, Munich, Bremen, Paderborn, Freiburg, Tuebingen, and Kaiserslautern.
Funded by the German Federal Ministry of Education and Research, this project investigated the effects of hardware errors on the software. These included single-event upsets that manifest themselves via bit flips in memory cells and registers. PROFORMA worked on models, techniques, and automatic tool chains that enable developers to formally prove whether or not hardware errors will affect particular tasks or certain functionality. Among other things, our contribution included extending the static analyzer Astrée to support taint analysis.
Consortium: AbsInt, TU Kaiserslautern, Verified Systems International.
2021 ITEA Award of Excellence, Special Vice-Chairman’s Award.
In this project, 26 partners from five countries developed a new open standard, eFMI, to exchange physics-based models between high-level modeling and simulation environments and low-level development tools for embedded code. The standard captures functional and non-functional quality requirements, supports traceability, and enables semi-automatic generation of code that is 25% faster than state-of-the-art handwritten code. The project additionally produced 33 use cases, 40 simulation configurations, and 13 tool prototypes.
Consortium: Bosch, Siemens, Volvo, Renault, Dassault, Maplesoft, CEA, Dana Belgium, FH Electronics, Grenoble INP, OSE Engineering, SOBEN, DLR, AbsInt, dSPACE, ETAS, ESI ITI, e:fs, PikeTec, Autoliv, RISE, Modelon, Universities of Linköping and Antwerp.
This project developed new, formally-motivated techniques that allow execution time, energy usage, security, and other important non-functional properties of parallel software to be treated as first-class citizens. The project brought together leading industrial and academic experts in parallelism, energy modeling, worst-case execution time analysis, non-functional property analysis, compilation, security, and task coordination. Results were evaluated using industrial use cases taken from the domains of computer vision, satellites, flying drones, medicine and cybersecurity. The three-year project was funded by the EU Horizon 2020 research and innovation programme.
Consortium: INRIA, Thales Alenia Space, Sky-Watch, IRIDA Labs, AbsInt, Universities of Amsterdam, Hamburg, Bristol, St. Andrews, and Southern Denmark.
A follow-up to the ARAMiS project. This time, the focus lay on optimization and advancement of the development processes, especially tools and platforms for the efficient usage of multicore technology. The applicability of all concepts and approaches was put to the test in industrial use cases from the automotive, avionics and industry automation domains. The three-year project was sponsored by the German Federal Ministry of Education and Research.
Consortium: DLR, Audi, Bosch, Continental, DENSO, Schaeffler, Airbus, General Electric, Hensoldt, Diehl Aerospace, Liebherr Aerospace, Siemens, WIKA Mobile Control, KSB, AbsInt, Accemic, ElektroBit, OpenSynergy, Silexica, Symtavision, Vector, Fraunhofer, KIT, OFFIS, ISP, fortiss, Universities of Augsburg and Kiel, TUs of Brunswick, Kaiserslautern, and Munich.
Funded by the German Federal Ministry of Education and Research,
this project developed an energy-efficient computer system for processing
sensor data in automated vehicles.
Consortium: Audi, DENSO, Infineon, Silicon Radar, SYSGO, AbsInt, Cadence, IHP, TU Brunswick.
This project investigated the challenges arising from the interdependence of safety, security and performance of safety-critical systems in transportation, medicine, space, and industrial control. AQUAS aimed at efficient solutions for the entire product life-cycle, and devised a coordinated engineering approach to address the ever-growing requirements on security and performance, while maintaining safety. Our contribution included combining safety analysis in the design phase with WCET analysis in the implementation phase, performing TimingProfiler analyses of Thales Alenia Space software, and using the static analyzer Astrée to analyze SYSGO’s PikeOS operating system.
Consortium: CEA, Thales, Thales Alenia Space, Siemens, Ansys Medini, RGB Medical Devices, SYSGO, AbsInt, All4tec, Clearsy, Brno University of Technology, Austrian Institute of Technology, Tecnalia, ITI, Intecs, Telecom ParisTech, TrustPort, Magillem, Integrasys, RheinMain University of Applied Sciences, Universities of London and L’Aquila.
With the aid of an all-new debugging system, this project collected and analyzed trace data in real time. To that end, an FPGA platform and several specialized synthesis applications were developed. The work was funded by the German Federal Ministry of Education and Research. Consortium: AbsInt, accemic, TU Darmstadt, University of Luebeck.
In this project, 38 partners from five countries devised an affordable and safe multi-core engineering methodology that allows the industry to develop mobility solutions with trustworthy new functions at competitive prices. Our contribution included improving the usability of the formally-verified CompCert compiler, raising the precision and efficiency of the static analyzer Astrée, extending the aiT WCET Analyzer to support the analysis of code running on the second generation of the Kalray MPPA processor, and extending Astrée to support AUTOSAR supplementary libraries, real-time POSIX, and sound analysis of data races and deadlocks.
Consortium: INRIA, Airbus, ENS, Esterel, Kalray, Thales, Safran (Snecma), Safran (Sagem), Daimler, BTC, Expleo, FZI, KIT, Model Engineering, OFFIS, Bosch, AbsInt, NXP, Recore, TNO, VDL, Verum Software, Arcticus, FindOut, KTH, Scania, Arçelik, Ericsson, Ford, Havelsan, KoçSistem, UNIT, Universities of Sorbonne, Kiel, Munich, Eindhoven, Twente, and Mälardalen.
This project developed a holistic approach for programming heterogeneous multicore and many-core architectures using automatic parallelization of model-based real-time applications. ARGO enhanced WCET-aware automatic parallelization by a cross-layer programming approach combining automatic tool-based and user-guided parallelization, thus reducing the need for expertise in programming parallel heterogeneous architectures. Among other things, our contribution included porting our flagship product aiT to Xentium, as well as supplying aiT for LEON3 with a memory-access counting extension.
Consortium: KIT, DLR, Dassault, Fraunhofer, TEU of Western Greece, emmtrix, AbsInt, University of Rennes 1.
This project enabled effective and efficient validation and verification of embedded systems, by combining advanced model-based testing technologies with static analysis and verification techniques. Led by Daimler and funded by the European ARTEMIS Joint Undertaking, the project brought together 39 partners from nine countries.
Consortium: Daimler, Airbus, Infineon, IBM, Thales, Dassault, Volvo, Siemens, CEA, ENS, Fraunhofer, BTC, ENEA, PikeTec, MBtech, OFFIS, Ansaldo, Leonardo, Selex, Ricardo, ALES, AMET, AVL LIST, All4tec, Alstom, Elvior, Alenia Aermacchi, Alten, Virtual Vehicle Research, KTH, Austrian Institute of Technology, Universities of Aalborg and Mälardalen, TUs of Munich and Graz.
Funded by the German Federal Ministry of Education and Research, this research project demonstrated the usability of multicore technology in safety-critical applications and improved the technological basis for increased safety, efficiency, and comfort in the automotive, avionics, and rail transportation domains. Our contribution included developing a new static analysis type for multi-core architectures, to automatically recognize accesses to shared resources.
Consortium: KIT, Audi, BMW, Bosch, Continental, Daimler, Airbus, Symtavision, SYSGO, Vector, AbsInt, OFFIS, and 18 others.
Contribute your expertise. Benefit from ours. Get in touch.
A mid-term project funded by the German Federal Ministry of Education and Research. It improved and integrated the project partners’ formal verification techniques for C and VHDL programs, thus increasing the overall benefit of formal verification, especially for the automotive industry.
Consortium: AbsInt, TU Kaiserslautern.
This project devised and built a system that prevents delays in the execution of safety-critical software, lowers development costs and reduces complexity. The project was partially funded by the European Commission under the 7th Framework Programme for Information and Communications Technologies. Consortium: The Open Group, TU Denmark, AbsInt, GMV, Intecs, TU Eindhoven, TU Vienna, University of York.
This project worked out a methodology for the development of complex critical applications, notably for many-core and multicore processors. This included a DOL-critical tool chain, Network-on-Chip tools, a code-generation tool chain for Kalray MPPA, and runtime environment tools. The project was funded by the European Commission under the 7th Framework Programme for Information and Communications Technologies. Consortium: Thales, Kalray, ARTTIC, Université Joseph Fourier, AbsInt, ETH Zurich, Uppsala University, TU Brunswick.
This project established a unique European virtual center of excellence, combining competencies from electrical engineering, computer science, applied mathematics and control theory, and covering all aspects of embedded-systems design from theory through to applications.
Our cluster: Compilers and Timing Analysis
Partners: ST Microelectronics, AbsInt, TU Vienna, RWTH Aachen, Universities of Mälardalen, Saarland, Dortmund and York.
The goal of this European-funded project from the ARTEMIS Joint Undertaking was to boost the cost efficiency of embedded-system development, safety processes, and certification. CESAR pursuited a multi-domain approach, integrating large enterprises, suppliers, SMEs, vendors of cross sectoral domains, and leading research organizations.
Consortium: AVL LIST, Airbus, Infineon, DLR, Thales, Safran, Siemens, ABB, Hitachi, Volvo, Fiat, Delphi, Dassault, Esterel, CEA, CNRS, INRIA, ONERA, Selex, NTNU, KTH, SINTEF, BTC Embedded Systems, Fraunhofer, AbsInt, OFFIS, alenia, Danieli Automation, Virtual Vehicle Research, Critical Software, Acciona Construccion, Tecnalia, Auvation Software, Hellenic Aerospace Industry, Universities of Oxford, Manchester, Athens, Thessaloniki, Trieste, and Bologna.
This project addressed the specification, transition and exchange of relevant timing information throughout different steps of the AUTOSAR-based development process and tool chain. This was achieved using the Timing Augmented Description Language, TADL2, that offers capabilities for symbolic time expressions modeling, probabilistic timing information, and timing constraints applied on mode definitions and aligned with EAST-ADL and AUTOSAR timing models. Our contribution included integrating the aiT WCET Analyzers and the static analyzer Astrée with TargetLink from dSPACE.
Consortium: Volvo, INRIA, Delphi, Continental, Bosch, Rapita Systems, Arcticus, dSPACE, AbsInt, Symtavision, Inchron, RealTime-at-Work, Time Critical Networks, Chalmers University of Technology, Universities of Brunswick, Paderborn, and Mälardalen.
A follow-up to Interest, within European Commission’s 7th Framework Programme on Research, Technological Development and Demonstration. This time the project partners created an open interoperable toolchain that fulfills the needs of the industry for designing and prototyping embedded systems. 17 interfaces between 11 tools were implemented, enabling the creation of 14 new product prototypes already before the project was completed.
Consortium: Sysgo, Symtavision, AbsInt, CEA, Esterel,
Atego, Evidence, TTTech. The work results were evaluated by industrial
partners that included Airbus, Thales, Magneti Marelli, and Siemens Rail Automation.
In the final project report, Airbus stated that its use of the Interested tool chain resulted in a 48% reduction in overall project effort. Thales reported a 25% reduction in effort, and Siemens reduced project costs by 20%. CEA’s initial development costs were reduced by 40% and on-going maintenance costs by 69%, while Magneti Marelli reported a 50% time saving.
A three-year focused-research project within the European Commission’s 7th Framework Programme on Research, Technological Development and Demonstration. Steered by Airbus and Bosch, the project improved the design and development methods for safety-critical embedded systems, by developing architectural concepts that support the derivation of timing guarantees for hard real-time systems, and providing the corresponding architectural platforms. Our contribution included extending the aiT WCET Analyzer with UCB (Useful Cache Block) analysis, and extending the XTC (XML Timing Cookies) format to allow the transfer of UCB analysis results and cache-content information to scheduling tools.
Consortium: Saarland University, Swiss Federal Institute of Technology, TU Dortmund, University of Bologna, Scuola Superiore Sant’Anna, AbsInt, EADS Airbus, Bosch.
A research project funded by the European Space Agency ESA under the basic Technology Research Programme, and a follow-up project to PEAL2 (Prototype Execution-time Analyser for LEON). This time, the project partners investigated how software running on a processor with cache can achieve maximum performance while remaining testable, predictable and analyzable. The work was done with particular reference to the LEON, which is widely used in space applications. Our contribution included porting our flagship product aiT WCET Analyzer to support LEON.
Consortium: University of Padua, Thales Alenia Space, Rapita Systems, AdaCore, AbsInt.
A middle-term research project focused on creation of a continuous development process for embedded systems which allows formal verification of safety-critical real-time aspects.
Consortium: AbsInt, DFKI, Symtavision, ScopeSET, aicas allerton, TUs Dresden, Brunswick, and Munich.
This long-term project developed and supported industrially applicable techniques for software specification, design, and development. Particular emphasis was put on methods supporting the development of software for communication and control applications.
Uppsala University, Mälardalen University, SICS, ABB, Ericsson, Volvo, IAR, T-Mobile UK, AbsInt, Telelogic, Arcticus, Cross Country Systems, ENEA, ESAB, Mecel, Mobile Arts, Prover Technology, TIDORUM, UPAAL, Validation, WM Data Validation, Virustech, Volcano Communication Technologies, ESAB Welding Equipment.
A research project within the European Commission’s 7th Framework Programme on Research, Technological Development and Demonstration. The aim was to combine available timing tools, thus strengthening the European lead in the timing-analysis area. ALL-TIMES successfully enabled interoperability of various tools from SMEs and universities, and developed integrated tool chains using open tool frameworks and interfaces.
Consortium: Mälardalen University, AbsInt, TU Vienna, Symtavision, Gliwa, Rapita Systems.
This project significantly improved the integration and interoperability of various tools for embedded-software development, in addition to developing novel techniques for system-level and node-level analysis of nonfunctional properties such as worst-case execution timing, stack usage and schedulability. Our contribution included the integration of aiT and StackAnalyzer with SCADE, ASCET, SymTA/S, and RT-Druid.
Consortium: AbsInt, Esterel, ETAS, Symtavision, Evidence, DecomSys, Unis.
A two-year project supported by the ITEA2 program (Information Technology for European Advancement). It focused on the improvement, integration, and dissemination of product-based software verification techniques.
Consortium: CS Information Systems, Airbus, AbsInt, Daimler, Esterel, Thales, CEA, Peugeot Citroën, Continental, EADS, ENS, ONERA, Fraunhofer FIRST, GTD Spain, Institut für Bahntechnik, Saarland University, TUs of Munich and Madrid.
This project identified, quantified and certified resource-bounded code in a domain-specific high-level programming language for real-time embedded systems. Using formal models of resource consumption as a basis, the project developed static analyses for time and space consumption and assessed these against realistic applications for embedded systems. Consortium: University of St. Andrews, Heriot-Watt University, AbsInt, Ludwig-Maximillian University, LASMEA.
A long-term research project focused on creation of methods and tools which allow persistent formal verification of the design of integrated computer systems. Among other things, from 2007 to 2010 researchers from the Verisoft XT project partnered up with Microsoft to verify code from Hyper-V, a multi-core x64 hypervisor, using a verifier for concurrent C code.
Consortium and partners: BMW, University of Saarland, AbsInt, DFKI, Max Planck Institute for Computer Science, Audi, Infineon, Bosch, Microsoft, Sysgo, TÜV Süd, OneSpin Solutions, Universities of Bremen, Freiburg, and Koblenz, TU Kaiserslautern, TU Munich, ESG, Sirrix, and others.
A shared-cost research and technology development project of the European IST Programme, focused on validation of critical avionics software. Our contribution included creating the first market-ready version of our flagship product aiT for static analysis of the worst-case execution time of tasks in real-time systems. Consortium: Airbus France, ENS, AbsInt, PolySpace Technologies, CEA, CNRS-LIX, Universities of Copenhagen, Tel-Aviv, Saarland, and Trier.
|SYSGO||AQUAS, TwinSpace, MORAL, Scale4Edge, Interested, EMPHASE, ARAMiS, ARAMiS II, Verisoft XT, TRISTAN|
|TU Munich||ASSUME, Scale4Edge, SuReal, ES_PASS, MBAT, ARAMiS II, Verisoft, Verisoft XT, TRISTAN|
|Bosch||ASSUME, Scale4Edge, PREDATOR, EMPHYSIS, Verisoft XT, ARAMiS, ARAMiS II, TRISTAN, TIMMO-2-USE|
|DLR, German Aerospace Center||ARGO, CESAR, QSMA, Scale4Edge, EMPHYSIS, ARAMiS II, Verisoft, Verisoft XT|
until the 2016 takeover by Luxoft
|ALL-TIMES, SuReal, Interest, Interested, ARAMiS, ARAMiS II, TIMMO-2-USE|
|Infineon Technologies||CESAR, Scale4Edge, EMPHASE, Verisoft, Verisoft XT, TRISTAN|
|Saarland University||Verisoft, Verisoft XT, artist2, DAEDALUS, PREDATOR, ES_PASS|
|Fraunhofer Societies and Institutes|
incl. Fraunhofer FIRST, Fraunhofer Institute for Integrated Circuits, Fraunhofer Society for Applied Research
|MBAT, ARAMiS II, CESAR, TRISTAN, ARGO, ES_PASS|
|TU Kaiserslautern||Scale4Edge, Verisoft XT, FORTE, FORTISSIMO, PROFORMA, ARAMiS II|
|OFFIS, Oldenburg Institute for Information Technology||ASSUME, CESAR, MBAT, ARAMiS, ARAMiS II, Verisoft|
|Siemens||CESAR, EMPHYSIS, MBAT, ARAMiS II, Scale4Edge|
|TU Brunswick||SuReal, CERTAINTY, EMPHASE, ARAMiS II, TIMMO-2-USE|
|TU Darmstadt||CONIRAS, Scale4Edge, Verisoft, Verisoft XT, TRISTAN|
Airbus Defense and Space, Airbus Operations
|CESAR, MBAT, ARAMiS, ARAMiS II|
|Daimler||ASSUME, ES_PASS, MBAT, ARAMiS|
|KIT, Karlsruhe Institute of Technology||ARGO, ASSUME, ARAMiS, ARAMiS II|
|Audi||EMPHASE, Verisoft XT, ARAMiS, ARAMiS II|
|Accemic||CONIRAS, ARAMiS II, TRISTAN|
|BTC Embedded Systems||ASSUME, CESAR, MBAT|
|Continental||ARAMiS, ARAMiS II, TIMMO-2-USE|
|DFKI, German Research Center for Artificial Intelligence||Verisoft, Verisoft XT, SuReal|
|emmtrix Technologies||ARGO, QSMA, TwinSpace|
|FZI, Karlsruhe Research Center for Information Technology||ASSUME, FreeSBee, Scale4Edge|
|IHP, Leibniz Institute for High-Performance Microelectronics||MORAL, Scale4Edge, EMPHASE|
|OneSpin Solutions||Verisoft, Verisoft XT, FORTISSIMO|
|University of Luebeck||CONIRAS, TwinSpace, ARAMiS II|
|DENSO||EMPHASE, ARAMiS II|
|e:fs TechHub||TwinSpace, EMPHYSIS|
|EPOS Embedded Code & Power Systems||Scale4Edge, TRISTAN|
|Max Planck Institute for Computer Science||Verisoft, Verisoft XT|
|MINRES Technologies||Scale4Edge, TRISTAN|
|University of Augsburg||TwinSpace, ARAMiS II|
|University of Bremen||Verisoft XT, Scale4Edge|
|University of Freiburg||Scale4Edge, Verisoft XT|
|University of Kiel||ASSUME, ARAMiS II|
|University of Koblenz||Verisoft, Verisoft XT|
|University of Paderborn||Scale4Edge, TIMMO-2-USE|
|Tensor Embedded||TwinSpace, TRISTAN|
|TU Clausthal||QSMA, TwinSpace|
|TU Dortmund||PREDATOR, artist2|
|TU Dresden||Scale4Edge, SuReal|
|Vector Informatik||ARAMiS, ARAMiS II|
|Ansys Medini Technologies||AQUAS|
|CARIAD — Automotive Software for Volkswagen||TwinSpace|
|Diehl Aerospace||ARAMiS II|
|Eclipse Foundation Europe||TRISTAN|
|fortiss Research Institute of Bavaria||ARAMiS II|
|General Electric||ARAMiS II|
|HM, Munich University of Applied Sciences||Scale4Edge|
|Institut für Bahntechnik||ES_PASS|
|Kasper & Oswald||FreeSBee|
|Liebherr Aerospace||ARAMiS II|
|LMU, Ludwig Maximilian University of Munich||EmBounded|
|Model Engineering Solutions||ASSUME|
|RheinMain University of Applied Sciences||AQUAS|
|Thales Transport Solutions Deutschland||ES_PASS|
|Timing Architects||ARAMiS II|
|TÜV Süd||Verisoft XT|
|University of Cottbus-Senftenberg||TwinSpace|
|University of Trier||DAEDALUS|
|University of Tuebingen||Scale4Edge|
|Verified Systems International||PROFORMA|
|WIKA Mobile Control||ARAMiS II|
|CEA, Commission for Atomic Energy and Alternative Energies||AQUAS, CESAR, DAEDALUS, Interested, ES_PASS, MBAT, EMPHYSIS, TRISTAN|
incl. Thales AVS, Thales Alenia Space France, Thales Six GTS, Thales Global Services, Thales DIS Design Services
|AQUAS, ASSUME, CESAR, Interested, ES_PASS, MBAT, CERTAINTY, TRISTAN|
Airbus Operations, Airbus Defence & Space, EADS Airbus
|ASSUME, CESAR, Interested, ES_PASS, MBAT, DAEDALUS, PREDATOR|
|Esterel Technologies||ASSUME, CESAR, Interest, Interested, ES_PASS|
|ENS||ASSUME, DAEDALUS, ES_PASS, MBAT|
INRIA Rennes, INRIA Sophia Antipolis
|ASSUME, CESAR, TeamPlay, TIMMO-2-USE|
|Dassault||CESAR, MBAT, EMPHYSIS|
Safran Aircraft Engines (Snecma), Safran Electronics & Defense (Sagem), Safran Helicopter Engines, Safran Landing Systems
|Siemens Industry Software||AQUAS, EMPHYSIS|
|ST Microelectronics||TRISTAN, artist2|
|All4tec, Alliance pour les Technologies de l’Informatique||MBAT, AQUAS|
|CNRS, National Center for Scientific Research||CESAR|
|Continental Automotive France||ES_PASS|
|CS Systèmes d’Information||ES_PASS|
EADS Astrium, EADS Innovation Works
|Institut Mines-Telecom, Telecom ParisTech||AQUAS|
|Institut National Polytechnique de Toulouse||ES_PASS|
|Institut National Polytechnique de Grenoble||EMPHYSIS|
|LASMEA, University Blaise-Pascal, Clermont-Ferrand||EmBounded|
|Magillem Design Services||AQUAS|
|NXP Semiconductors France||TRISTAN|
|Office National d’Études et de Recherches Aerospatiales||CESAR|
|Peugeout Citroën Automobiles||ES_PASS|
|Robert Bosch France||TRISTAN|
|Scilab Enterprises, Dassault Systèmes||ARGO|
|Université Joseph Fourier||CERTAINTY|
|University of Rennes 1||ARGO|
|University of Sorbonne||ASSUME|
|Mälardalen University||ALL-TIMES, ASSUME, ASTEC, artist2, MBAT, TIMMO-2-USE|
incl. Volvo Technology, Volvo Teknisk Utveckling, Volvo Personvagnar
|CESAR, MBAT, ASTEC, EMPHYSIS, TIMMO-2-USE|
|KTH, Royal Institute of Technology||ASSUME, CESAR, MBAT|
|Arcticus Systems||ASSUME, ASTEC, TIMMO-2-USE|
|Uppsala University||ASTEC, CERTAINTY|
|RISE SICS||EMPHYSIS, ASTEC|
|ABB Automation Technologies||ASTEC|
|Chalmers University of Technology||TIMMO-2-USE|
|Cross Country Systems||ASTEC|
|Dassault Systems Sweden||EMPHYSIS|
|ESAB Welding Equipment||ASTEC|
|Time Critical Networks||TIMMO-2-USE|
|WM Data Validation||ASTEC|
|Volcano Communication Technologies||ASTEC|
|Università di Bologna||CESAR, PREDATOR, TRISTAN|
|Selex Sistemi Integrati||CESAR, MBAT|
|Intecs Solutions||AQUAS, T-CREST|
|Alenia Aermacchi||MBAT, CESAR|
|Università degli studi dell’Aquila||AQUAS|
|Centro Ricerche FIAT||CESAR|
|Università degli studi di Trieste||CESAR|
|Scuola Superiore Sant’Anna||PREDATOR|
|E 4 Computer Engineering||TRISTAN|
|Politecnico di Torino||TRISTAN|
|University of Padua||COLA|
|Rapita Systems||ALL-TIMES, TIMMO-2-USE, COLA|
|University of St. Andrews||EmBounded, TeamPlay|
|University of York||artist2, T-CREST|
|Airbus UK||MBAT, CESAR|
|University of Bristol||TeamPlay|
|City, University of London||AQUAS|
|University of Manchester||CESAR|
|The Chancellor, Masters and Scholars of the University of Oxford||CESAR|
|TU/e, Eindhoven University of Technology||ASSUME, T-CREST|
|University of Twente||ASSUME, TRISTAN|
|University of Amsterdam||TeamPlay|
|NLR, Netherlands Aerospace Center||TRISTAN|
|NXP Semiconductors Netherlands||ASSUME|
|VDL Enabling Transport Solutions||ASSUME|
|Verum Software Tools||ASSUME|
|Vienna University of Technology||ALL-TIMES, T-CREST, artist2|
|AIT Austrian Institute of Technology||AQUAS, MBAT|
|AVL List||CESAR, MBAT|
|Infineon Technologies Austria||CESAR, MBAT|
|Virtual Vehicle Research||CESAR, MBAT|
|Siemens Austria||AQUAS, TRISTAN|
|TU Graz||MBAT, TRISTAN|
|Decomsys (now ElektroBit)||Interest|
|NXP Semiconductors Austria||TRISTAN|
|Thales Alenia Space||AQUAS, MORAL, COLA, TeamPlay|
|Tecnalia Research & Innovation||AQUAS, CESAR|
|Instituto Tecnológico de Informática||AQUAS|
|RGB Medical Devices||AQUAS|
|Aristotle University of Thessaloniki||CESAR|
|Hellenic Aerospace Industry||CESAR|
|National Technical University of Athens||CESAR|
|Technological Educational Institute of Western Greece||ARGO|
|Athina-Erevnitiko Kentro Kainotomias stis Technologies tis Pliroforias, ton Epikoinonion kai tis Gnosis||CESAR|
|KoçSistem Information and Communication Services||ASSUME|
|UNIT Information Technologies R&D||ASSUME|
|University of Copenhagen||DAEDALUS|
|University of Southern Denmark||TeamPlay|
|Danmarks Tekniske Universitet, Lyngby||T-CREST|
|Siemens Industry Software||EMPHYSIS|
|University of Antwerp||EMPHYSIS|
|The Open Group||T-CREST|
|IMEC, Interuniversity Microelectronics Center||TRISTAN|
|Nokia Solutions and Networks||TRISTAN|
|NTNU, Norwegian University of Science and Technology||CESAR|
|SINTEF, Independent Organisation for Applied Research, Technology and Innovation||CESAR|
|Brno University of Technology||AQUAS|
|Siemens Electronic Design Automation Israel||TRISTAN|
|Swiss Federal Institute of Technology, ETH Zurich||PREDATOR, CERTAINTY, TRISTAN|
|NXP Semiconductors Romania||TRISTAN|