Ongoing projects
- ARGO
WCET-aware parallelization of model-based applications for heterogeneous parallel systems
- ARAMiS II
Tools, platforms, and processes for the development of safety-critical multicore systems
- ASSUME
Affordable safe and secure mobility evolution
- AQUAS
Aggregated quality assurance for systems
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Media coverage
- Elektronik automotive 9/2018
“The Perfect Compiler”
- Funktionale Sicherheit 7/2015
“Multicore-CPUs in sicherheitskritischen
Echtzeitsystemen” (PDF)
- Elektronik automotive 3/2014
“Safely Excluding Serious Errors” (PDF)
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Recent publications
- Obtaining Worst-Case Execution Time Bounds on Modern Microprocessors (PDF, 900kB)
by D. Kästner, M. Pister, S. Wegener, and C. Ferdinand.
Embedded World Congress, Nuremberg, 2018.
- CompCert: Practical Experience on Integrating and Qualifying a Formally Verified Optimizing Compiler (PDF, 600kB)
by D. Kästner, J. Barrho, U. Wünsche, M. Schlickling, B. Schommer et al.,
in ERTS² 2018 — Embedded Real Time Software and Systems, January 2018, Toulouse, France. <hal-01643290>.
- B. Dreyer, C. Hochberger, A. Lange, S. Wegener and A. Weiss.
Continuous non-intrusive hybrid WCET estimation using waypoint graphs (PDF, 660kB).
Proceedings of the 16th International Workshop on Worst-Case Execution-Time Analysis (WCET 2016).
- H. Falk, S. Altmeyer, P. Hellinckx, B. Lisper, W. Puffitsch, C. Rochange, M. Schoeberl, R. Bo Sørensen, P. Waegemann and S. Wegener.
TACLeBench: a benchmark collection to support worst-case execution time research (PDF, 443kB).
Proceedings of the 16th International Workshop on Worst-Case Execution-Time Analysis (WCET 2016).
- M. Schoeberl, S. Abbaspour, B. Akesson, N. Audsley,
R. Capasso, J. Garside, K. Goossens, S. Goossens,
S. Hansen, R. Heckmann,
S. Hepp, B. Huber, A. Jordan, E. Kasapaki, J. Knoop,
Y. Li, D. Prokesch, W. Puffitsch, P. Puschner, A. Rocha,
C. Silva, J. Sparsø, and A. Tocchi.
T-CREST: time-predictable multi-core architecture for embedded systems.
Journal of Systems Architecture, 61/2015, pp. 449–471.
