a³ release 10.08

New target

StackAnalyzer for H8 now available.

Qualification Support Kits (QSKs)

  • New QSK available for the aiT module of a³ for LEON3 (gcc-3.4.4).
  • New QSK available for the StackAnalyzer module of H8 (including measurements).
  • Extended WCET QSK for MPC603e: added tests for local loop-bound specifications via source-file references.
  • Extended Stack QSK for M68020 by measurements.
  • Improvemens to all QSKs:
    • The QSK test procedures are now supported by a graphical user interface.
    • Extended QSKs by new tests for recently added AIS features.
    • Extended QSKs by new tests for recently added a³ GUI options.
    • All QSKs are now shipped with an additional report called “Software Verification Results”. This report is an acknowledgement that all tests have been successfully executed before the delivery.

a³ toolchain

  • zlib compression tuned for speed.
  • Improved speed of prediction-file base toolchain.

XTC handling

Fixed the issue with the very first XTC request not being answered under certain circumstances.


  • Folding all nodes will no longer cause the graph to be hidden.
  • Nodes found via the search dialog can now be made visible by double-clicking on the search result.
  • The number of graph folding operations has been reduced to a minimum.
  • Empty tooltips are no longer displayed.

a³ GUI

  • Improved reading of large DWARF debug info inside the GUI.
  • DWARF debug info and Sections info only created and loaded on demand.
  • Better cleanup of temporary files.
  • Better message handling for background threads such as disassembly writer.
  • Fixed disassembly problem that resulted in some routines not being shown in the GUI.
  • Added graphical visualization of the WCET contributions (see screenshot).
  • Show which analysis are to be run in the summary view.
  • Show error if specified machine description file does not exist.
  • Each information view uses the same filter dialog.
  • Highlighted errors in editor view are cleared upon re-running an analysis.
  • Improved search in the Graph view (see screenshot).
  • Added overwrite mode in the text editor.
  • Improved analysis overview: analyses can now be re-sorted via drag-and-drop.
  • All editor, message, and disassembly views can now be detached from the a³ GUI (see screenshot).
  • In the debug views, type information is now displayed in cases for which it was missing before.
  • Improved Disassembly view (see screenshot).
  • Fixed problem with Windows filenames and “Display source”.
  • In the WCET Contributions view, missing or unavailable analysis results are now marked as “n/a” rather than as “-1”.
  • The message window is no longer cleared upon analysis start unless expressly configured that way.
  • Improved the “Show applied annotation” feature. If the same AIS annotation is valid for several subsequent source-code lines, their buttons for jumping to the annotation are combined into a single one (see screenshot).
  • Code view has been renamed into Disassembly view for improved consistency.
  • “Disable visualization” applies to batch mode only.
  • H8: “CPU Variant” has been renamed into “Instruction Set”.
  • HCS12: clarified that register contents (not register addresses) have to be specified in the machine configuration dialog.
  • Minor general cleanups.


  • New annotation “skip target check” replaces the annotation “computed_target_feasible=1”.
  • Targets of indirect function calls can now be specified.
  • AIS expressions can now produce and process modulo information.
  • New operators “uint” and “sint” for casting arbitrary values to unsigned and signed integers of given bit width.
  • New operator “exactly ==” for comparing two sets of possible values.
  • New operator “exact” to test if a value is exact.
  • Special value NaN is replaced by (-inf .. inf).
  • The predicate “defined” that tested for NaN has been removed.
  • The “round” operation is now called “int”.
  • HC11/HCS12: annotations describing the effect of the swi instruction on stack and timing have been replaced by more generic ones.
  • V850: new annotations for software exceptions.
  • ARM7: flashes (with description in AIS) are supported again.
  • a³ with contexts: there can be more than one interproc specification.

Features that already existed in 10.04, but weren’t documented

  • a³ with timing and daan: execution times of code snippets excluded from analysis may be expressions.
  • a³ with timing: loops may have time bounds.
  • Annotations concerning memory areas:
    • New short form “position .. + n bytes”.
    • New form “position align + n bytes”.
    • New annotation “might contain data” for memory areas.
    • a³ where memory accesses are of importance: clarification about “ARRAY + 0 bytes”.


  • Reduced memory usage during DWARF debug info extraction.
  • GHS compiler: improved handling of data symbols containing path names. The symbols are now transformed in the same manner as routine symbols.
  • The decoder now warns about relocations (non-statically linked binaries or presence of dynamic link info).
  • Improved detection of read-only memory areas and the “is copied from” annotation.
  • Improved handling of the program-point annotation “<name> + <n> branch/conditional”.
  • Fixed issue with include paths for finding source files, if the path separators don’t match the ones of the used operating system or are mixed (/ vs. \).
  • C16x: fixed mnemonic for addresses in bit-addressable modes.
  • H8:
    • Improved decoding of jsr/jmp @@a8 with zeropage address indirection.
    • Improved mnemonics of several instructions.
  • HCS12:
    • Improved decoding of CPS instruction.
    • Improved switch table patterns.
    • Improved readability by using alias mnemonics for assembly instructions.
    • Support for xb-byte encodings for call instruction with computed call target.
  • M32: improved decoding of several instructions and their representation in the disassembly.
  • M68020: improved decoding of switch tables (XD Ada).
  • PCP2:
    • Support for DWARF line info.
    • Correct order of operands for exit instruction in decoded assembly string.
    • Improved decoding of load/store instructions.
    • Improved decoding of control-flow instructions.
    • Consistent assembly strings for immediate constants.
  • PPC:
    • Extension for switch table detection.
    • Improved decoding of switch tables for GCC.
    • MPC55xx: extended VLE instruction set to support the following instructions intended to improve the interrupt handler efficiency:
      • e_lmvgprw
      • e_stmvgprw
      • e_lmvsprw
      • e_stmvsprw
      • e_lmvsrrw
      • e_stmvsrrw
      • e_lmvcsrrw
      • e_stmvcsrrw
      • e_lmvdsrrw
      • e_stmvdsrrw
  • SPARC:
    • The annotations “condition ... is false if ...” and “condition ... is false make infeasible” now work for conditional branches with delay slots. This improves the analysis precision.
    • Improved decoding of switch tables (GNAT Ada compiler).
    • Improved handling of tail calls.
  • V850:
    • General improvements to decoding of V850 binaries.
    • Improved decoding of binaries comprising code holes.
    • Better decoding of computed branches and tail calls.
    • Handle “fetrap”, “syscall”, and “rie” as trap.
    • Improved resolving of indirect function pointers.
    • Improved detection of size information for stack frames embedded in the code segment for StackAnalyzer for V850/GHS.

Stack and value analysis

  • Value analysis is less strict with asserts annotations evaluated in speculative analysis contexts.
  • H8:
    • Improved precision for instructions such as sub.w.
    • General improvements.
  • HCS12: the value analysis now aborts when no memory map is specified. This check was previously done by the pipeline analysis.
  • V850:
    • Stack analysis now available for generic V850 E1/ES and E2 targets.
    • Improved handling of computed calls in stack analysis.
  • M68020: stack analysis now supports the STOP instruction.
  • PowerPC: improved precision of value analysis thanks to ranges for loop variables calculated by loop analysis.

Path analysis

  • New, improved implementation of the prediction-file based path analysis. The analysis is now faster, consumes less memory, and uses no swap files.
  • New, improved implementation of the prediction-file based path analysis using ILP which allows additional user constraints and persistence analysis.
  • Correct handling of address ranges above 0x8000000 in the count-accesses annotations.
  • Prediction-file based path analyses now support the TLB miss penalties.
  • Improve persistence analysis for not fully unrolled examples.

Cache and pipeline analysis

  • Improved May-Cache analysis.
  • Improved persistence analysis if multiple caches are used.
  • Local best case added to multiple targets.
  • The unrolling-consistency check for user-provided loop bounds is now also performed for default loop bounds, possibly resulting in more warnings such as “loop seems to have more iterations than specified”.
  • C16x:
    • Added support for C165UTAH.
    • The report file now includes the bus configuration.
  • PPC750: improved handling of write-triggered reads on write-back memory areas.
  • TriCore: improved handling of writes into external memory.
  • V850:
    • More user-friendly handling of memory accesses that target unknown memory regions (i.e. memory regions that are not specified in the AIS file).
    • Improved timing model with regard to prepare and dispose instructions.
    • Minor fix for memory map generation for V850E/FK3-H: the area 0x3fec664…0x3fec665 now correctly contains CAN1 module transmit history list register instead of being classified as a general programmable peripheral area.
    • Significantly improved performance and reduced memory consumption of the pipeline analysis.

Visualization and reporting

  • Output UCB results per “evaluated as” annotation.

Trace validation (used for QSKs)

  • Added optional validation by means of NEXUS-like measurements.
  • The user may now specify an address range for bus and queue event traces, limiting the scope of validation to events contained in that specific address range.