Dr.-Ing. Jörg Herter

Dr.-Ing. Jörg Herter

Curriculum vitæ

Jörg Herter studied Computer Science and received his Ph.D. on predictable dynamic memory allocation for hard real-time systems in 2014. He has been a research fellow at Saarland University and the University of Applied Sciences in Saarbrücken.

His current work is focused on functional safety and the formal validation and verification of safety-critical software.

Jörg Herter works as a Senior Technical Consultant for AbsInt. He teaches static program analysis, embedded systems technology, compiler construction, and mathematics at the Saarland University of Applied Sciences and Cooperative Education.

Jörg is also a lecturer at the University of Luxembourg and has been teaching at Saarland University and the Technical University of Kaiserslautern.

Selected publications

  • J. Herter, D. Kästner, C. Mallon, R. Wilhelm. Benchmarking Static Code Analyzers. In SAFECOMP’17: Proceedings of the International Conference on Computer Safety, Reliability and Security, Trento, 2017. Springer LNCS, Heidelberg.
  • J. Herter, C. Mallon, D. Kästner. Designing Test Suites for Benchmarking Static Code Analyzers. Embedded World Congress, Nürnberg, 2017.
  • J. Herter. Timing-Predictable Memory Allocation in Hard Real-Time Systems. PhD Thesis. Saarland University, 2014.
  • F. Haupenthal, J. Herter. PRADA: Predictable Allocations by Deferred Actions. Proceedings of the 13th International Workshop on Worst-Case Execution-Time Analysis (WCET 2013).
  • J. Herter, P. Backes, F. Haupenthal, J. Reineke. CAMA: A Predictable Cache-Aware Memory Allocator. Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS ’11), Porto, Portugal, July 2011.