Dr. Jörg Herter

Dr.-Ing. Jörg Herter

Curriculum vitæ

Jörg Herter studied Computer Science and received his Ph.D. on predictable dynamic memory allocation for hard real-time systems in 2014. He has been a research fellow at Saarland University and the University of Applied Sciences in Saarbruecken.

His current work is focused on functional safety and the formal validation and verification of safety-critical software.

Jörg Herter works as a Senior Technical Consultant for AbsInt, in addition to teaching static program analysis, embedded systems technology, compiler construction, and mathematics at the Saarland University of Applied Sciences and Cooperative Education. He is also a lecturer at the University of Luxembourg and has been teaching at the University of Saarland and the Technical University of Kaiserslautern.

Jörg Herter is also a frequent speaker at tradeshows, conferences, workshops, and other events all around the world.

Selected publications

  • Benchmarking Static Code Analyzers. J. Herter, D. Kästner, C. Mallon, R. Wilhelm. In SAFECOMP’17: Proceedings of the International Conference on Computer Safety, Reliability and Security, Trento, 2017. Springer LNCS, Heidelberg.
  • Designing Test Suites for Benchmarking Static Code Analyzers. J. Herter, C. Mallon, D. Kästner. Embedded World Congress, Nuremberg, 2017.
  • Timing-Predictable Memory Allocation in Hard Real-Time Systems.
    J. Herter. PhD Thesis. Saarland University, 2014.
  • PRADA: Predictable Allocations by Deferred Actions. F. Haupenthal, J. Herter. Proceedings of the 13th International Workshop on Worst-Case Execution-Time Analysis (WCET 2013, ECRTS Satellite Workshop).
  • CAMA: A Predictable Cache-Aware Memory Allocator. J. Herter, P. Backes, F. Haupenthal, J. Reineke. Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS ’11), Porto, Portugal, July 2011.