Simon Wegener

Simon Wegener

Curriculum vitæ

Simon Wegener completed his Master’s degree in computer science at the University of Saarland. He joined AbsInt in 2011, specializing in static analysis of binary code. Since then, he has contributed to a multitude of German and European research projects and authored or co-authored a number of peer-reviewed publications on static timing analysis.

Selected publications

  • Sound Signal Flow Analysis for C/C++. D. Kästner, L. Mauborgne, S. Hahn, S. Wilhelm, J. Herter, C. Cullmann, C. Ferdinand. Embedded World Congress 2025, Nuremberg.
  • Multi-Core WCET Analysis Using Non-Intrusive Continuous Observation. D. Kästner, G. Gebhard, M. Pister, S. Wegener, C. Ferdinand, A. Schulz, M. Sachenbacher, M. Leucker, A. Weiss. In ERTS 2024: Embedded Real Time Software and Systems, 12th European Congress, Toulouse, June 2024.
  • Satisfying Timing Requirements for Safety-Critical Real-Time Software. D. Kästner, C. Hümbert, G. Gebhard, M. Pister, S. Wegener, C. Ferdinand. Embedded World Congress 2024, Nuremberg.
  • Non-intrusive, continuous trace-based monitoring and its applications for system correctness, safety, and resilience. M. Leucker, M. Sachenbacher, A. Schulz, S. Wegener, A. Weiss. DX’23: 34th International Workshop on Principles of Diagnosis, Loma Mar, CA.
  • EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications. S. Wegener, K. K. Nikov, J. Nunez-Yanez, K. Eder. WCET 2023: 21st International Workshop on Worst-Case Execution Time Analysis.
  • The TeamPlay Project: Analysing and Optimising Time, Energy, and Security for Cyber-Physical Systems. B. Rouxel, C. Brown, E. Ebeid, K. Eder, H. Falk, C. Grelck, J. Holst, S. Jadhav, Y. Marquer, M. Martinez de Alejandro et al. DATE 2023: Design, Automation & Test in Europe.
  • Whole-System Analysis for Memory Protection and Management. F. Bräunling, S. Wegener, D. Kästner, I. Stilkerich. In ERTS 2022: Embedded Real Time Software and Systems, 11th European Congress, Toulouse, June 2022.
  • Taming Timing — Combining Static Analysis with Non-Intrusive Tracing to Compute WCET Bounds on Multicore Processors. D. Kästner, C. Hümbert, G. Gebhard, M. Pister, S. Wegener, C. Ferdinand. Embedded World Congress 2021, Virtual Conference.
  • Using Generic Software Components for Safety-Critical Embedded Systems — An Engineering Framework. F. Bräunling, R. Hilbrich, S. Wegener, I. Stilkerich, D. Kästner. In ERTS 2020: 10th European Congress on Embedded Real Time Systems.
  • TimeWeaver: A Tool for Hybrid Worst-Case Execution Time Analysis. 19th International Workshop on Worst-Case Execution Time Analysis, WCET 2019, Stuttgart.
  • Embedded Program Annotations for WCET Analysis. B. Schommer, C. Cullmann, G. Gebhard, X. Leroy, M. Schmidt, S. Wegener. Proceedings of the WCET 2018, Barcelona, 8:1–8:13.
  • Online analysis of debug trace data for embedded systems.
    DATE 2018: Design, Automation & Test in Europe.
  • Obtaining worst-case execution time bounds on modern microprocessors (PDF, 900kB). D. Kästner, M. Pister, S. Wegener, and C. Ferdinand. Embedded World Congress, Nuremberg, 2018.
  • Towards Multicore WCET Analysis.
    WCET 2017: 17th International Workshop on Worst-Case Execution Time Analysis, Dubrovnik.
  • Hardware Support for Histogram-Based Performance Analysis of Embedded Systems.
    ISORC 2017: 20th International IEEE Symposium on Real-Time Distributed Computing.
  • Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs.
    WCET 2016: 16th International Workshop on Worst-Case Execution Time Analysis, Toulouse.
  • Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement.
    26th Euromicro Conference on Real-Time Systems, 2014.
  • Computing Same Block Relations for Relational Cache Analysis.
    WCET 2012: 12th International Workshop on Worst-Case Execution Time Analysis, Pisa.