A cache block is useful at a given instruction if it is
The number of useful cache blocks, then, is an upper bound for the number of additional cache misses caused by an interrupt at the instruction.
The output of the analysis is the maximum number of useful cache blocks taken over all program points of the analyzed task.
If the maximum penalty to handle a cache miss in CPU cycles is given, the maximum cache-related time penalty of an interrupt/preemption of the task is computed as the product of the number of useful cache blocks and the penalty for handling a single cache miss.
The analysis output appears in aiT’s message window, the textual report file, and the XML report file. Apart from this global maximum, it is also possible to obtain UCB analysis results for a given basic block, which are then accessible via an additional information window in the control-flow graph.
The UCB analysis is also available in TimingProfiler for PowerPC.